#define CHIP_RESET_ADDR 0x980d
#define AUTO_ZERO_ADDR   0X00CB
#define AUTO_ZERO_LONG_MASK  0X7FFF
#define AUTO_ZERO_SHORT_MASK  0XBFFF
#define BP_ADDR   0X11
#define BP_ADDR_PAM4 0X11
#define BP_CTU_MASK  0XDFFF
#define BP_CTU_MASK_PAM4 0XDFFF
#define CNTDR_CORR_ADDR   0X92
#define CNTR_TARGET_FINAL_ADDR 0X02
#define CNTR_TARGET_FINAL_ADDR_NRZ 0X102
#define CNTR_TARGET_FINAL_ADDR_PAM4 0X02
#define CNTR_TARGET_FINAL_MASK  0X0
#define CNTR_TARGET_FINAL_MASK_NRZ 0XF
#define CNTR_TARGET_FINAL_MASK_PAM4 0X0
#define CNTR_TARGET_INIT_ADDR 0X01
#define CNTR_TARGET_INIT_ADDR_NRZ 0X102
#define CNTR_TARGET_INIT_ADDR_PAM4 0X01
#define CNTR_TARGET_INIT_MASK  0X0
#define CNTR_TARGET_INIT_MASK_NRZ 0XF
#define CNTR_TARGET_INIT_MASK_PAM4 0X0
#define CTLE_EN_ADDR   0X21
#define CTLE_EN_ADDR_NRZ 0X14D
#define CTLE_EN_ADDR_PAM4 0X21
#define CTLE_EN_MASK  0XFF7F
#define CTLE_EN_MASK_NRZ 0X7FFF
#define CTLE_EN_MASK_PAM4 0XFF7F
#define CTLE_FINE_ADDR   0XF9
#define CTLE_FINE_MASK  0XE3FF
#define CTLE_GAIN1_ADDR   0XF5
#define CTLE_GAIN1_MASK  0X80FF
#define CTLE_GAIN2_ADDR   0XF5
#define CTLE_GAIN2_MASK  0XFF80
#define CTLE_MAP0_ADDR   0X4A
#define CTLE_MAP0_ADDR_NRZ 0X178
#define CTLE_MAP0_ADDR_PAM4 0X4A
#define CTLE_MAP1_ADDR   0X49
#define CTLE_MAP1_ADDR_NRZ 0X177
#define CTLE_MAP1_ADDR_PAM4 0X49
#define CTLE_MAP2_ADDR   0X48
#define CTLE_MAP2_ADDR_NRZ 0X176
#define CTLE_MAP2_ADDR_PAM4 0X48
#define CTLE_VAL_ADDR   0X21
#define CTLE_VAL_ADDR_NRZ 0X14E
#define CTLE_VAL_ADDR_PAM4 0X21
#define CTLE_VAL_MASK  0XFF8F
#define CTLE_VAL_MASK_NRZ 0XC7FF
#define CTLE_VAL_MASK_PAM4 0XFF8F
#define DAC_SEL_ADDR   0X28
#define DAC_SEL_ADDR_NRZ 0X17F
#define DAC_SEL_ADDR_PAM4 0X28
#define DAC_SEL_MASK  0XFE1F
#define DAC_SEL_MASK_NRZ 0XFFF
#define DAC_SEL_MASK_PAM4 0XFE1F
#define DAC_SEL_OW_ADDR   0X21
#define DAC_SEL_OW_ADDR_NRZ 0X14F
#define DAC_SEL_OW_ADDR_PAM4 0X21
#define DAC_SEL_OW_MASK  0XF0FF
#define DAC_SEL_OW_MASK_NRZ 0XFFF
#define DAC_SEL_OW_MASK_PAM4 0XF0FF
#define DAC_SEL_OW_EN_ADDR   0X21
#define DAC_SEL_OW_EN_ADDR_NRZ 0X14C
#define DAC_SEL_OW_EN_ADDR_PAM4 0X21
#define DAC_SEL_OW_EN_MASK  0XEFFF
#define DAC_SEL_OW_EN_MASK_NRZ 0XFF7F
#define DAC_SEL_OW_EN_MASK_PAM4 0XEFFF
#define DELTA_PH_OW_ADDR   0X12
#define DELTA_PH_OW_ADDR_PAM4 0X12
#define DELTA_PH_OW_EN_MASK  0XDFFF
#define DELTA_PH_OW_EN_MASK_PAM4 0XDFFF
#define DELTA_PH_OW_VAL_MASK  0XE03F
#define DELTA_PH_OW_VAL_MASK_PAM4 0XE03F
#define DFE_DELTA_ADDR   0X10D
#define DFE_DELTA_ADDR_NRZ 0X10D
#define DFE_DELTA_MASK  0XFF80
#define DFE_DELTA_MASK_NRZ 0XFF80
#define DFE_F1_ADDR   0X12B
#define DFE_F1_ADDR_NRZ 0X12B
#define DFE_F1_MASK  0XFF80
#define DFE_F1_MASK_NRZ 0XFF80
#define DFE_F2_ADDR   0X12C
#define DFE_F2_ADDR_NRZ 0X12C
#define DFE_F2_MASK  0X80FF
#define DFE_F2_MASK_NRZ 0X80FF
#define DFE_F3_ADDR   0X12C
#define DFE_F3_ADDR_NRZ 0X12C
#define DFE_F3_MASK  0XFF80
#define DFE_F3_MASK_NRZ 0XFF80
#define DFE_FREEZE_MASK  0X7FFF
#define DFE_FREEZE_MASK_NRZ 0X7FFF
#define DFE_FREEZE_MASK_PAM4 0X7FFF
#define DFE_FREEZE_EN_ADDR   0X0F
#define DFE_FREEZE_EN_ADDR_NRZ 0X109
#define DFE_FREEZE_EN_ADDR_PAM4 0X0F
#define EDGE1_ADDR   0XE5
#define EDGE1_ADDR_PAM4 0XE5
#define EDGE1_MASK  0XFFF
#define EDGE1_MASK_PAM4 0XFFF
#define EDGE2_ADDR   0XE5
#define EDGE2_ADDR_PAM4 0XE5
#define EDGE2_MASK  0XF0FF
#define EDGE2_MASK_PAM4 0XF0FF
#define EDGE3_ADDR   0XE5
#define EDGE3_ADDR_PAM4 0XE5
#define EDGE3_MASK  0XFF0F
#define EDGE3_MASK_PAM4 0XFF0F
#define EDGE4_ADDR   0XE5
#define EDGE4_ADDR_PAM4 0XE5
#define EDGE4_MASK  0XFFF0
#define EDGE4_MASK_PAM4 0XFFF0
#define EM_ADDR   0X92
#define EM_B0_MASK  0XDFFF
#define EM_BN1_MASK  0XEFFF
#define EM_BN2_MASK  0XF7FF
#define EM_BN3_MASK  0XFBFF
#define EM_CNTR1_EN  0XFFFE
#define EM_CNTR2_EN  0XFFFD
#define EM_CNTR3_EN  0XFFFB
#define EM_CNTR4_EN  0XFFF7
#define EM_CNTR5_EN  0XFFEF
#define EM_CNTR6_EN  0XFFDF
#define EM_CNTR7_EN  0XFFBF
#define EM_CNTR8_EN  0XFF7F
#define EM_CNTR_ADDR   0X93
#define EM_CNTR_FREEZE_MASK  0XFEFF
#define EM_CNTR_ZERO_SEL_MASK  0XFF7F
#define EM_DIR_MASK  0XFDFF
#define EM_FIXED_PATTERN_MODE_MASK  0X3FFF
#define EM_MODE_EN_ADDR   0X0F
#define EM_MODE_EN_BIT  0X7FFF
#define EM_POSTE_DISABLE_MASK  0XFFBF
#define EXT_RCH_EN_ADDR   0XEC
#define EXT_RCH_EN_ADDR_PAM4 0XEC
#define EXT_RCH_EN_MASK  0XFEFF
#define EXT_RCH_EN_MASK_PAM4 0XFEFF
#define EXT_RCH_PARAM1_MASK  0XFF1F
#define EXT_RCH_PARAM1_MASK_PAM4 0XFF1F
#define EXT_RCH_PARAM2_MASK  0XFFE3
#define EXT_RCH_PARAM2_MASK_PAM4 0XFFE3
#define EYE_MARGIN_ADDR   0X32
#define EYE_MARGIN_ADDR2   0X33
#define EYE_MARGIN_ADDR2_PAM4 0X33
#define EYE_MARGIN_ADDR_PAM4 0X32
#define EYE_MINUS_MARGIN_LOWER_MASK  0XFF
#define EYE_MINUS_MARGIN_UPPER_MASK  0XFFF0
#define EYE_MINUS_MARGIN_UPPER_MASK_PAM4 0XFFF0
#define EYE_PLUS_MARGIN_MASK  0XF
#define EYE_PLUS_MARGIN_MASK_PAM4 0XF
#define EYE_READ_ADDR   0X38
#define EYE_READ_ADDR_NRZ 0X12A
#define EYE_READ_ADDR_PAM4 0X38
#define EYE_READ_MASK  0XF000
#define EYE_READ_MASK_NRZ 0XF000
#define EYE_READ_MASK_PAM4 0XF000
#define F1OVER3_ADDR   0X04
#define F1OVER3_ADDR_PAM4 0X04
#define F1OVER3_MASK  0XF01F
#define F1OVER3_MASK_PAM4 0XF01F
#define FFE_DELAY1234_CTRL_ADDR   0XEF
#define FFE_DELAY1234_CTRL_ADDR_PAM4 0XEF
#define FFE_DELAY1_MASK  0XFFF
#define FFE_DELAY1_MASK_PAM4 0XFFF
#define FFE_DELAY2_MASK  0XF0FF
#define FFE_DELAY2_MASK_PAM4 0XF0FF
#define FFE_DELAY3_MASK  0XFF0F
#define FFE_DELAY3_MASK_PAM4 0XFF0F
#define FFE_DELAY4_MASK  0XFFF0
#define FFE_DELAY4_MASK_PAM4 0XFFF0
#define FFE_DELAY5678_CTRL_ADDR   0XEE
#define FFE_DELAY5678_CTRL_ADDR_PAM4 0XEE
#define FFE_DELAY5_MASK  0XFFF
#define FFE_DELAY5_MASK_PAM4 0XFFF
#define FFE_DELAY6_MASK  0XF0FF
#define FFE_DELAY6_MASK_PAM4 0XF0FF
#define FFE_DELAY7_MASK  0XFF0F
#define FFE_DELAY7_MASK_PAM4 0XFF0F
#define FFE_DELAY8_MASK  0XFFF0
#define FFE_DELAY8_MASK_PAM4 0XFFF0
#define FFE_DELAY9_MASK  0XFFF
#define FFE_DELAY9_MASK_PAM4 0XFFF
#define FFE_DELAY9_CTRL_ADDR   0XED
#define FFE_DELAY9_CTRL_ADDR_PAM4 0XED
#define FFE_EN_ADDR   0XF7
#define FFE_EN_ADDR_PAM4 0XF7
#define FFE_EN_MASK  0XBFFF
#define FFE_EN_MASK_PAM4 0XBFFF
#define FFE_GAIN1_ADDR   0XF1
#define FFE_GAIN1_ADDR_PAM4 0XF1
#define FFE_GAIN1_MASK  0XF0FF
#define FFE_GAIN1_MASK_PAM4 0XF0FF
#define FFE_GAIN2_ADDR   0XF1
#define FFE_GAIN2_ADDR_PAM4 0XF1
#define FFE_GAIN2_MASK  0XFFF0
#define FFE_GAIN2_MASK_PAM4 0XFFF0
#define FFE_PO11_MASK  0XFDFF
#define FFE_PO11_MASK_PAM4 0XFDFF
#define FFE_PO12_MASK  0XFEFF
#define FFE_PO12_MASK_PAM4 0XFEFF
#define FFE_PO13_MASK  0XFF7F
#define FFE_PO13_MASK_PAM4 0XFF7F
#define FFE_PO14_MASK  0XFFBF
#define FFE_PO14_MASK_PAM4 0XFFBF
#define FFE_POL_ADDR   0XF0
#define FFE_POL_ADDR_PAM4 0XF0
#define FFE_POL_MASK  0XFC3F
#define FFE_POL_MASK_PAM4 0XFC3F
#define FFE_TAP1_ADDR   0XF2
#define FFE_TAP1_ADDR_PAM4 0XF2
#define FFE_TAP1_MASK  0XFF
#define FFE_TAP1_MASK_PAM4 0XFF
#define FFE_TAP1_EN_MASK  0XF7FF
#define FFE_TAP1_EN_MASK_PAM4 0XF7FF
#define FFE_TAP234_ADDR   0XF2
#define FFE_TAP234_ADDR_PAM4 0XF2
#define FFE_TAP234_MASK  0XFF00
#define FFE_TAP234_MASK_PAM4 0XFF00
#define FFE_TAP2_ADDR   0XF3
#define FFE_TAP2_ADDR_PAM4 0XF3
#define FFE_TAP2_MASK  0XFF
#define FFE_TAP2_MASK_PAM4 0XFF
#define FFE_TAP2_EN_MASK  0XDFFF
#define FFE_TAP2_EN_MASK_PAM4 0XDFFF
#define FFE_TAP34_ADDR   0XF3
#define FFE_TAP34_ADDR_PAM4 0XF3
#define FFE_TAP34_MASK  0XFF00
#define FFE_TAP34_MASK_PAM4 0XFF00
#define FFE_TAP3_ADDR   0XF4
#define FFE_TAP3_ADDR_PAM4 0XF4
#define FFE_TAP3_MASK  0XFF
#define FFE_TAP3_MASK_PAM4 0XFF
#define FFE_TAP3_EN_MASK  0X7FFF
#define FFE_TAP3_EN_MASK_PAM4 0X7FFF
#define FFE_TAP4_ADDR   0XF4
#define FFE_TAP4_ADDR_PAM4 0XF4
#define FFE_TAP4_MASK  0XFF00
#define FFE_TAP4_MASK_PAM4 0XFF00
#define FFE_TAP4_EN_MASK  0XBFFF
#define FFE_TAP4_EN_MASK_PAM4 0XBFFF
#define FW_CMD_ADDR   0X9815
#define FW_CMD_DETAIL_ADDR   0X9816
#define FW_CRC_CMD   0XF001
#define FW_DEBUG_CMD   0XB000
#define FW_EYEMON_PROG_CMD   0X2000
#define FW_EYEMON_READ_CMD   0X3000
#define FW_EYEMON_START_CMD   0X1000
#define FW_HALT_ADDR   0X9815
#define FW_HALT_CMD   0XD000
#define FW_HALT_EN   0XD000
#define FW_HALT_STATUS   0X0D00
#define FW_HASH_CMD   0XF000
#define FW_LOAD_MAGIC_WORD_ADDR   0X9814
#define FW_LOAD_MAGIC_WORD_NRZ 0X6A6A
#define FW_LOAD_MAGIC_WORD_PAM4  0X5A5A
#define FW_LOAD_MAGIC_WORD_PAM4 0X5A5A
#define FW_NRZ_DATA_RATE_1   7
#define FW_NRZ_DATA_RATE_10   1
#define FW_NRZ_DATA_RATE_16   11
#define FW_NRZ_DATA_RATE_25   3
#define FW_NRZ_DATA_RATE_28   5
#define FW_PAM4_DATA_RATE_37   6
#define FW_PAM4_DATA_RATE_53   9
#define FW_PAM4_DATA_RATE_56   10
#define FW_REG_READ_CMD   0XE010
#define FW_REG_VALUE_ADDR   0X9812
#define FW_REG_WRITE_CMD   0XE020
#define FW_TUNING_CTRL_ADDR   0X980F
#define FW_TUNING_CTRL_BACKGROUND_CAL_MASK 0XFBFF
#define FW_TUNING_CTRL_BACKGROUND_CAL_MASK_PAM4  0XFBFF
#define FW_TUNING_CTRL_BACKGROUND_CAL_MASK_PAM4 0XFBFF
#define FW_TUNING_CTRL_CTLE_MODE_MASK  0XFFFE
#define FW_TUNING_CTRL_CTLE_MODE_MASK_NRZ 0XFFFE
#define FW_TUNING_CTRL_CTLE_MODE_MASK_PAM4  0XFFF
#define FW_TUNING_CTRL_CTLE_MODE_MASK_PAM4 0XFFF
#define FW_TUNING_CTRL_DATA_RATE_MASK  0XFFC7
#define FW_TUNING_CTRL_DATA_RATE_MASK_PAM4  0XFFC7
#define FW_TUNING_CTRL_DATA_RATE_MASK_PAM4 0XFFC7
#define FW_TUNING_CTRL_FFE_ADAPT_DIS_MASK  0XF7FF
#define FW_TUNING_CTRL_FFE_ADAPT_DIS_MASK_PAM4  0XF7FF
#define FW_TUNING_CTRL_FFE_ADAPT_DIS_MASK_PAM4 0XF7FF
#define FW_TUNING_CTRL_FFE_ADAPT_EN_MASK  0XFDFF
#define FW_TUNING_CTRL_FFE_ADAPT_EN_MASK_PAM4  0XFDFF
#define FW_TUNING_CTRL_FFE_ADAPT_EN_MASK_PAM4 0XFDFF
#define FW_TUNING_CTRL_GO_MASK  0X7FFF
#define FW_TUNING_CTRL_LT_TX_SWAP  0XFFBF
#define FW_TUNING_CTRL_OPTICS_MODE_MASK  0XFFFD
#define FW_TUNING_CTRL_OPTICS_MODE_MASK_NRZ 0XFFFD
#define FW_TUNING_CTRL_RX_DEBUG_MODE_MASK 0XFFEF
#define FW_TUNING_CTRL_RX_DEBUG_MODE_MASK_NRZ 0XFFEF
#define FW_TUNING_CTRL_TEMP_TRACK_EN_MASK  0XFFFB
#define FW_TUNING_CTRL_TEMP_TRACK_EN_MASK_NRZ 0XFFFB
#define FW_TUNING_START_BP_NRZ 'BP1'
#define FW_TUNING_START_BP_PAM4 'BP1'
#define FW_TUNING_START_STATE_NRZ 1
#define FW_TUNING_START_STATE_PAM4 3
#define FW_TUNING_STATUS_ADDR   0X9811
#define FW_TUNING_STATUS_ADDR_NRZ 0X9811
#define FW_TUNING_STATUS_ADDR_PAM4 0X9811
#define FW_TUNING_STATUS_DONE_MASK  0XFFFB
#define FW_TUNING_STATUS_DONE_MASK_NRZ 0XFFF7
#define FW_TUNING_STATUS_DONE_MASK_PAM4 0XFFFB
#define FW_TUNING_STATUS_DONE_LINK_ALMOST_RDY_MASK  0XFFFD
#define FW_TUNING_STATUS_DONE_LINK_ALMOST_RDY_MASK_NRZ 0XFFFD
#define FW_TUNING_STATUS_DONE_LINK_ALMOST_RDY_MASK_PAM4 0XFFFD
#define FW_TUNING_STATUS_DONE_LINK_NOT_RDY_MASK  0XFFF7
#define FW_TUNING_STATUS_DONE_LINK_NOT_RDY_MASK_NRZ 0XFFF7
#define FW_TUNING_STATUS_DONE_LINK_NOT_RDY_MASK_PAM4 0XFFF7
#define FW_TUNING_STATUS_IN_PROGRESS_MASK  0XFFFE
#define FW_TUNING_STATUS_IN_PROGRESS_MASK_NRZ 0XFFFE
#define FW_TUNING_STATUS_IN_PROGRESS_MASK_PAM4 0XFFFE
#define FW_TUNING_STATUS_TEMP_TRACK_MASK  0XFFFB
#define FW_TUNING_STATUS_TEMP_TRACK_MASK_NRZ 0XFFFB
#define FW_WATCHDOG_TIMER_ADDR   0X9810
#define GPI0_MASK 0XFFFE
#define GPI1_MASK 0XFFFD
#define GPI_ADDR   0X9806
#define GPO0_MASK 0XFFFE
#define GPO1_MASK 0XFFFD
#define GPO_ADDR   0X9807
#define ITER_S4_ADDR   0X06
#define ITER_S4_ADDR_PAM4 0X06
#define ITER_S4_MASK  0XFFF
#define ITER_S4_MASK_PAM4 0XFFF
#define ITER_S6_ADDR   0X09
#define ITER_S6_ADDR_PAM4 0X09
#define ITER_S6_MASK  0XFFF0
#define ITER_S6_MASK_PAM4 0XFFF0
#define KR_SM_COEF_0_MASK  0XFFC0
#define KR_SM_COEF_1_MASK  0XC0FF
#define KR_SM_COEF_ADDR   0XB3
#define KR_SM_COEF_M1_MASK  0XC0FF
#define KR_SM_COEF_M2_MASK  0XFFC0
#define KR_SM_COEF_M_ADDR   0XB4
#define KR_SM_COEF_SEL_ADDR   0XA0
#define KR_SM_COEF_SEL_MASK  0XFFEF
#define LANE_RESET_ADDR 0X00
#define LANE_RESET_ADDR_NRZ 0X181
#define LANE_RESET_ADDR_PAM4 0X00
#define LANE_RESET_MASK 0X7FFF
#define LANE_RESET_MASK_NRZ 0XF7FF
#define LANE_RESET_MASK_PAM4 0X7FFF
#define LOOP_BACK_EN_ADDR   0X9803
#define LOOP_BACK_EN_MASK  0X7FFF
#define NRZ_10G_MODE_ADDR   0X179
#define NRZ_10G_MODE_ADDR_NRZ 0X179
#define NRZ_10G_MODE_MASK 0XFFFE
#define NRZ_10G_MODE_MASK_NRZ 0XFFFE
#define NRZ_BB_MODE_ADDR 0X179
#define NRZ_BB_MODE_MASK 0XFFBF
#define NRZ_DELTA_ADAPT_EN_ADDR 0X101
#define NRZ_DELTA_ADAPT_EN_MASK 0XBFFF
#define NRZ_PRBS_CNT_ADDR 0X166
#define NRZ_PRBS_CNT_RST_ADDR 0X161
#define NRZ_PRBS_CNT_RST_MASK 0X7FFF
#define NRZ_PRBS_MODE_SEL_ADDR 0X161
#define NRZ_PRBS_MODE_SEL_MASK 0XCFFF
#define NRZ_RDY_MASK  0XFFFB
#define NRZ_SD_MASK  0XFFF7
#define NRZ_SD_RDY_ADDR   0X12E
#define OWEN_BLW_OFFSET_MASK  0XBFFF
#define OW_BLW_OFFSET_MASK  0XC0FF
#define OW_MU_OFFSET_ADDR   0X87
#define OW_MU_OFFSET_ADDR_PAM4 0X87
#define OW_MU_OFFSET_MASK  0XF9FF
#define OW_MU_OFFSET_MASK_PAM4 0XF9FF
#define PAM4MM_F0_FGT_ADDR   PAM4MM_MM_DTL_EN_ADDR
#define PAM4MM_F0_FGT_MASK  0XC0FF
#define PAM4MM_F1_FGT_ADDR   PAM4MM_MM_DTL_EN_ADDR
#define PAM4MM_F1_FGT_MASK  0XFFC0
#define PAM4MM_LEV_UPDATE_ADDR   PAM4MM_MM_DTL_EN_ADDR
#define PAM4MM_LEV_UPDATE_MASK  0XFFBF
#define PAM4MM_MM_DTL_EN_ADDR   0X0094
#define PAM4MM_MM_DTL_EN_MASK  0X7FFF
#define PAM4MM_MM_POL_ADDR   PAM4MM_MM_DTL_EN_ADDR
#define PAM4MM_MM_POL_MASK  0XFF7F
#define PAM4MM_QUALI_MODE_ADDR   PAM4MM_MM_DTL_EN_ADDR
#define PAM4MM_QUALI_MODE_MASK  0XBFFF
#define PAM4MM_QUANT_LEV0_ADDR   0X0095
#define PAM4MM_QUANT_LEV0_MASK  0XC0FF
#define PAM4MM_QUANT_LEV10_ADDR   0X009A
#define PAM4MM_QUANT_LEV10_MASK  0XC0FF
#define PAM4MM_QUANT_LEV11_ADDR   PAM4MM_QUANT_LEV10_ADDR
#define PAM4MM_QUANT_LEV11_MASK  0XFFC0
#define PAM4MM_QUANT_LEV1_ADDR   PAM4MM_QUANT_LEV0_ADDR
#define PAM4MM_QUANT_LEV1_MASK  0XFFC0
#define PAM4MM_QUANT_LEV2_ADDR   0X0096
#define PAM4MM_QUANT_LEV2_MASK  0XC0FF
#define PAM4MM_QUANT_LEV3_ADDR   PAM4MM_QUANT_LEV2_ADDR
#define PAM4MM_QUANT_LEV3_MASK  0XFFC0
#define PAM4MM_QUANT_LEV4_ADDR   0X0097
#define PAM4MM_QUANT_LEV4_MASK  0XC0FF
#define PAM4MM_QUANT_LEV5_ADDR   PAM4MM_QUANT_LEV4_ADDR
#define PAM4MM_QUANT_LEV5_MASK  0XFFC0
#define PAM4MM_QUANT_LEV6_ADDR   0X0098
#define PAM4MM_QUANT_LEV6_MASK  0XC0FF
#define PAM4MM_QUANT_LEV7_ADDR   PAM4MM_QUANT_LEV6_ADDR
#define PAM4MM_QUANT_LEV7_MASK  0XFFC0
#define PAM4MM_QUANT_LEV8_ADDR   0X0099
#define PAM4MM_QUANT_LEV8_MASK  0XC0FF
#define PAM4MM_QUANT_LEV9_ADDR   PAM4MM_QUANT_LEV8_ADDR
#define PAM4MM_QUANT_LEV9_MASK  0XFFC0
#define PAM4_DFE_READ_ADDR   0X2F
#define PAM4_DFE_READ_ADDR_PAM4 0X2F
#define PAM4_DFE_READ_MASK  0XF
#define PAM4_DFE_READ_MASK_PAM4 0XF
#define PAM4_DFE_SEL_ADDR   0X88
#define PAM4_DFE_SEL_ADDR_PAM4 0X88
#define PAM4_DFE_SEL_MASK  0XFF0F
#define PAM4_DFE_SEL_MASK_PAM4 0XFF0F
#define PAM4_PRBS_CNT_ADDR 0X50
#define PAM4_PRBS_CNT_RST_ADDR 0X43
#define PAM4_PRBS_CNT_RST_MASK 0XFFFE
#define PAM4_PRBS_MODE_SEL_ADDR 0X43
#define PAM4_PRBS_MODE_SEL_MASK 0XFF9F
#define PAM4_RDY_MASK  0X7FFF
#define PAM4_SD_MASK  0XFF7F
#define PAM4_SD_RDY_ADDR   0X6A
#define PAM4_TAP_ADDR   0X40
#define PAM4_TAP_ADDR_PAM4 0X40
#define PAM4_TAP_MASK  0XFF80
#define PAM4_TAP_MASK_PAM4 0XFF80
#define PAM4_TAP_SEL_ADDR   0X45
#define PAM4_TAP_SEL_ADDR_PAM4 0X45
#define PAM4_TAP_SEL_MASK  0XFF87
#define PAM4_TAP_SEL_MASK_PAM4 0XFF87
#define PLL_DIV4_ADDR   0XFF
#define PLL_DIV4_MASK  0XFFDF
#define PLL_LVCOCAP0_MASK  0XFFFD
#define PLL_LVCOCAP0_DDR   0XFA
#define PLL_LVCOCAP_ADDR   0XFC
#define PLL_LVCOCAP_MASK  0X3FF
#define PLL_LVCOCAP_DDR   0XFC
#define PLL_N_MASK  0X7F
#define PLL_N_DDR   0XFD
#define PRBS_CNT_ADDR_HI 0X4E
#define PRBS_CNT_ADDR_HI_NRZ 0X166
#define PRBS_CNT_ADDR_HI_PAM4 0X4E
#define PRBS_CNT_ADDR_LO 0X4F
#define PRBS_CNT_ADDR_LO_NRZ 0X167
#define PRBS_CNT_ADDR_LO_PAM4 0X4F
#define PRBS_CNT_MAX   0XFFFFFFFF
#define PRBS_CNT_MAX_PAM4 0XFFFFFFFF
#define PRBS_CNT_RST_ADDR 0X43
#define PRBS_CNT_RST_ADDR_NRZ 0X161
#define PRBS_CNT_RST_ADDR_PAM4 0X43
#define PRBS_CNT_RST_MASK 0XFDFF
#define PRBS_CNT_RST_MASK_NRZ 0X7FFF
#define PRBS_CNT_RST_MASK_PAM4 0XFDFF
#define PRBS_MODE_SEL_ADDR 0X43
#define PRBS_MODE_SEL_ADDR_NRZ 0X161
#define PRBS_MODE_SEL_ADDR_PAM4 0X43
#define PRBS_MODE_SEL_MASK 0XFF9F
#define PRBS_MODE_SEL_MASK_NRZ 0XCFFF
#define PRBS_MODE_SEL_MASK_PAM4 0XFF9F
#define RAM0_ADDR   0X9808
#define RAM0_FADIO_MASK  0XFF
#define RAM0_REDENIO_MASK  0XFF7F
#define RAM1_ADDR   0X9809
#define RAM1_FADIO_MASK  0XFF
#define RAM1_REDENIO_MASK  0XFF7F
#define RAM2_ADDR   0X980A
#define RAM2_FADIO_MASK  0XFF
#define RAM2_REDENIO_MASK  0XFF7F
#define REG_BLWC_EN_MASK  0X7FFF
#define REG_BLWC_MU_MASK  0XFFF8
#define REG_BLW_EAGLE_ADDR   0X7C
#define REG_BLW_PHOENIX_ADDR   0X7B
#define REG_BLW_POLARITY_INVERT_MASK  0XFFF7
#define REG_COMP_CHECK_MASK  0XC0FF
#define REG_DIV_ST2_MASK  0XDFFF
#define REG_FREQ_MULTIPLIER_MASK  0XFFE7
#define REG_FREQ_MUP_MASK  0XFF1F
#define REG_FREQ_SHIFT_SEL_MASK  0XFFF8
#define REG_FW_DATA0 0X9F00
#define REG_LOCK_PHASE_EAGLE_ADDR   0X7B
#define REG_LOCK_PHASE_FLIP_MASK  0XEFFF
#define REG_LOCK_PHASE_PHOENIX_ADDR   0X7A
#define REG_MM_BLWC_EN_MASK  0X7FFF
#define REG_OWEN_LOCK_PHASE_MASK  0XFF7F
#define REG_OW_LOCK_PHASE_MASK  0XFF80
#define REG_SPD_ADDR   0X7A
#define REG_SPD_SEL1_MASK  0XFCFF
#define REG_SPD_SEL2_MASK  0XF3FF
#define REG_SPEED_MODE_SEL_ST2_MASK  0X3FFF
#define REG_TED12_EN_MASK  0XBFFF
#define REG_TED12_QUAL_OFF_MASK  0XDFFF
#define REG_TED_ADDR   0X79
#define RESTART_COUNTER_ADDR   0X14F
#define RESTART_COUNTER_ADDR_NRZ 0X14F
#define RESTART_COUNTER_MASK  0XFFE0
#define RESTART_COUNTER_MASK_NRZ 0XFFE0
#define RX_NRZ_POL_ADDR  0X161
#define RX_NRZ_POL_MASK 0XBFFF
#define RX_PAM4_EN_ADDR   0X41
#define RX_PAM4_EN_MASK  0X7FFF
#define RX_PAM4_POL_ADDR 0X43
#define RX_PAM4_POL_MASK 0XFF7F
#define SD_MASK  0XFF7F
#define SD_MASK_NRZ 0XFFF7
#define SD_MASK_PAM4 0XFF7F
#define SD_RDY_ADDR   0X6A
#define SD_RDY_ADDR_NRZ 0X12E
#define SD_RDY_ADDR_PAM4 0X6A
#define SM_ADDR   0X28
#define SM_ADDR_PAM4 0X28
#define SM_MASK  0XC1FF
#define SM_MASK_PAM4 0XC1FF
#define SM_BP1_MASK  0X7FFF
#define SM_BP1_MASK_PAM4 0X7FFF
#define SM_BP2_MASK  0XBFFF
#define SM_BP2_MASK_PAM4 0XBFFF
#define SM_CTRL_ADDR   0X11
#define SM_CTRL_ADDR_NRZ 0X10B
#define SM_CTRL_ADDR_PAM4 0X11
#define SM_CTRL_BP1_EN_MASK  0X7FFF
#define SM_CTRL_BP1_EN_MASK_NRZ 0X7FFF
#define SM_CTRL_BP1_EN_MASK_PAM4 0X7FFF
#define SM_CTRL_BP1_STATE_ADDR   0X11
#define SM_CTRL_BP1_STATE_ADDR_NRZ 0X10B
#define SM_CTRL_BP1_STATE_ADDR_PAM4 0X11
#define SM_CTRL_BP1_STATE_MASK  0XE0FF
#define SM_CTRL_BP1_STATE_MASK_NRZ 0XE0FF
#define SM_CTRL_BP1_STATE_MASK_PAM4 0XE0FF
#define SM_CTRL_BP2_EN_MASK  0XBFFF
#define SM_CTRL_BP2_EN_MASK_NRZ 0XFF7F
#define SM_CTRL_BP2_EN_MASK_PAM4 0XBFFF
#define SM_CTRL_BP2_STATE_ADDR   0X11
#define SM_CTRL_BP2_STATE_ADDR_NRZ 0X10B
#define SM_CTRL_BP2_STATE_ADDR_PAM4 0X11
#define SM_CTRL_BP2_STATE_MASK  0XFFE0
#define SM_CTRL_BP2_STATE_MASK_NRZ 0XFFE0
#define SM_CTRL_BP2_STATE_MASK_PAM4 0XFFE0
#define SM_CTRL_CONTINUE_ADDR   0X11
#define SM_CTRL_CONTINUE_ADDR_NRZ 0X10C
#define SM_CTRL_CONTINUE_ADDR_PAM4 0X11
#define SM_CTRL_CONTINUE_MASK  0XDFFF
#define SM_CTRL_CONTINUE_MASK_NRZ 0X7FFF
#define SM_CTRL_CONTINUE_MASK_PAM4 0XDFFF
#define SM_CTRL_STEP_ADDR   0X11
#define SM_CTRL_STEP_ADDR_PAM4 0X11
#define SM_CTRL_STEP_MASK  0XFFBF
#define SM_CTRL_STEP_MASK_NRZ 0XFFFB
#define SM_CTRL_STEP_MASK_PAM4 0XFFBF
#define SM_CTRL_STEP_EN_ADDR   0X11
#define SM_CTRL_STEP_EN_ADDR_NRZ 0X10C
#define SM_CTRL_STEP_EN_ADDR_PAM4 0X11
#define SM_CTRL_STEP_EN_MASK  0XFF7F
#define SM_CTRL_STEP_EN_MASK_NRZ 0XFFF7
#define SM_CTRL_STEP_EN_MASK_PAM4 0XFF7F
#define SM_STATE_NUM_MASK  0XC1FF
#define SM_STATE_NUM_MASK_NRZ 0XE0FF
#define SM_STATE_NUM_MASK_PAM4 0XC1FF
#define SM_STATUS_ADDR   0X28
#define SM_STATUS_ADDR_NRZ 0X10D
#define SM_STATUS_ADDR_PAM4 0X28
#define SM_STATUS_BP1_MASK  0X7FFF
#define SM_STATUS_BP1_MASK_NRZ 0X7FFF
#define SM_STATUS_BP1_MASK_PAM4 0X7FFF
#define SM_STATUS_BP2_MASK  0XBFFF
#define SM_STATUS_BP2_MASK_NRZ 0XBFFF
#define SM_STATUS_BP2_MASK_PAM4 0XBFFF
#define TH_INI_MASK  0X80FF
#define TH_INI_MASK_PAM4 0X80FF
#define TIMER_S1_ADDR   0X00
#define TIMER_S1_ADDR_PAM4 0X00
#define TIMER_S1_MASK  0XFFE0
#define TIMER_S1_MASK_PAM4 0XFFE0
#define TIMER_S3_ADDR   0X03
#define TIMER_S3_ADDR_PAM4 0X03
#define TIMER_S3_MASK  0X7FF
#define TIMER_S3_MASK_PAM4 0X7FF
#define TIMER_S5_MASK  0X87FF
#define TIMER_S5_MASK_PAM4 0X87FF
#define TIMER_S_ADDR   0X07
#define TIMER_S_ADDR_PAM4 0X07
#define TX_MAIN_ADDR   0XA9 
#define TX_MAIN_MASK  0XFF
#define TX_MAIN_SCALE_MASK  0XFFF7
#define TX_POL_ADDR 0XA0
#define TX_POL_MASK 0XFFDF
#define TX_POST1_ADDR   0XA7 
#define TX_POST1_MASK  0XFF
#define TX_POST1_SCALE_MASK 0XFFFB
#define TX_POST2_ADDR   0XA5 
#define TX_POST2_MASK  0XFF
#define TX_POST2_SCALE_MASK 0XFFFD
#define TX_PRE1_ADDR   0XAB 
#define TX_PRE1_MASK  0XFF
#define TX_PRE1_SCALE_MASK  0XFFEF
#define TX_PRE2_ADDR   0XAD 
#define TX_PRE2_MASK  0XFF
#define TX_PRE2_SCALE_MASK  0XFFDF
#define TX_TAPS_SCALE_ADDR   0XAF
#define TX_TAPS_SUM_LIMIT   31
#define TX_TEST_PATT_ADDR_1 0XA4
#define TX_TEST_PATT_ADDR_2 0XA3
#define TX_TEST_PATT_ADDR_3 0XA2
#define TX_TEST_PATT_ADDR_4 0XA1
#define TX_TEST_PATT_CTRL_ADDR 0XA0
#define TX_TEST_PATT_CTRL_MASK 0X7FFF
#define TX_TEST_PATT_SEL_ADDR 0XA0
#define TX_TEST_PATT_SEL_MASK 0XFCFF
#define VHICURRENT_INPUTBUF_ADDR   0X00CB
#define VHICURRENT_INPUTBUF_MASK  0XFFFD
#define XCORR_CNTDR_ERR_RLT_ADDR   0X0093
#define XCORR_CNTDR_ERR_RLT_MASK  0X0
#define XCORR_CNTDR_READ_MUX_ADDR   XCORR_C_QUA_POL_ADDR
#define XCORR_CNTDR_READ_MUX_MASK  0XFFF0
#define XCORR_CNTF_FREEZE_DC_ADDR   XCORR_GATE_ADDR
#define XCORR_CNTF_FREEZE_DC_MASK  0XFFEF
#define XCORR_CNTR_FREEZE_ADDR   0X0074
#define XCORR_CNTR_FREEZE_MASK  0X7FFF
#define XCORR_CNTR_FREEZE_TAP_ADDR   XCORR_GATE_ADDR
#define XCORR_CNTR_FREEZE_TAP_MASK  0XFFF7
#define XCORR_C_QUA_POL_ADDR   0X0090
#define XCORR_C_QUA_POL_MASK  0X7FFF
#define XCORR_FIXED_PAT_ADDR   XCORR_C_QUA_POL_ADDR
#define XCORR_FIXED_PAT_MASK  0XFF0F
#define XCORR_GATE_ADDR   0X0091
#define XCORR_GATE_MASK  0XFEFF
#define XCORR_RESULT_CLR_DC_ADDR    XCORR_GATE_ADDR
#define XCORR_RESULT_CLR_DC_MASK   0XFFFB
#define XCORR_RESULT_CLR_TAP_ADDR    XCORR_GATE_ADDR
#define XCORR_RESULT_CLR_TAP_MASK   0XFFFD
#define XCORR_SHIFT_TAP_ADDR   XCORR_C_QUA_POL_ADDR
#define XCORR_SHIFT_TAP_MASK   0X8FFF
#define XCORR_TIMER_SET_TAP_ADDR    XCORR_C_QUA_POL_ADDR
#define XCORR_TIMER_SET_TAP_MASK   0XF0FF
#define XCORR_TIMER_START_CLR_TAP_ADDR    XCORR_GATE_ADDR
#define XCORR_TIMER_START_CLR_TAP_MASK    0XFFFE

#define TX_NRZ_EN_ADDR  0XB0
#define TX_NRZ_EN_MASK  0XFFFD
#define TX_NRZ_PRBS_EN_ADDR  0XB0
#define TX_NRZ_PRBS_EN_MASK  0XF7FF
#define TX_NRZ_PRBS_GEN_EN_ADDR  0XB0
#define TX_NRZ_PRBS_GEN_EN_MASK  0XBFFF
#define TX_PAM4_PRBS_GEN_EN_ADDR  0XA0
#define TX_PAM4_PRBS_GEN_EN_MASK  0XBFFF
#define RX_NRZ_EN_ADDR  0X179
#define RX_NRZ_EN_MASK  0XFFDF
#define RX_PAM4_EN_ADDR  0X41
#define RX_PAM4_EN_MASK  0X7FFF
#define TX_MSB_LSB_ADDR  0XAF
#define TX_MSB_LSB_MASK  0XFBFF
#define RX_MSB_LSB_ADDR  0X43
#define RX_MSB_LSB_MASK  0X7FFF
#define TX_GC_EN_ADDR  0XAF
#define TX_GC_EN_MASK  0XFDFF
#define RX_GC_EN_ADDR  0X42
#define RX_GC_EN_MASK  0XFFFE
#define TX_PC_EN_ADDR  0XAF
#define TX_PC_EN_MASK  0XFEFF
#define RX_PC_EN_ADDR  0X42
#define RX_PC_EN_MASK  0XFFFD

#define AUTO_NEG_CONTROL_ADDR 0x8000
#define AUTO_NEG_BASE_PAGE_15_0_ADDR 0x8010
#define AUTO_NEG_BASE_PAGE_31_16_ADDR 0x8011
#define AUTO_NEG_BASE_PAGE_47_32_ADDR 0x8012
#define AUTO_NEG_MSG_PAGE_15_0_CONSORT_ADDR 0x80F0
#define AUTO_NEG_MSG_PAGE_31_16_CONSORT_ADDR 0x80F1
#define AUTO_NEG_MSG_PAGE_47_32_CONSORT_ADDR 0x80F2
#define AUTO_NEG_UF_PAGE_15_0_CONSORT_ADDR 0x80F3
#define AUTO_NEG_UF_PAGE_31_16_CONSORT_ADDR 0x80F4
#define AUTO_NEG_UF_PAGE_47_32_CONSORT_ADDR 0x80F5

#define LINK_TRAINING_CONTROL_ADDR 0x8100
#define LINK_TRAINING_STATUS_ADDR 0x8104
#define POLYNOMIAL_CONFIG_ADDR 0x814E

#define AUTO_NEG_LINK_TRAINING_STATUS_ADDR 0x8201

#define PCS_LINK_STATUS_BIT_31_16_ADDR 0x8209
#define PCS_LINK_STATUS_BIT_15_0_ADDR 0x820A

#define ARG_ADDR 0x8300
#define AA_OVERWRITE 0x8302

#define AUTO_NEG_TX_BASE_PAGE_15_0_ADDR 0x8311
#define AUTO_NEG_TX_BASE_PAGE_31_16_ADDR 0x8312
#define AUTO_NEG_TX_BASE_PAGE_47_32_ADDR 0x8313
#define AUTO_NEG_TX_MSG_PAGE_15_0_ADDR 0x8314
#define AUTO_NEG_TX_MSG_PAGE_31_16_ADDR 0x8315
#define AUTO_NEG_TX_MSG_PAGE_47_32_ADDR 0x8316
#define AUTO_NEG_TX_UF_PAGE_15_0_ADDR 0x8317
#define AUTO_NEG_TX_UF_PAGE_31_16_ADDR 0x8318
#define AUTO_NEG_TX_UF_PAGE_47_32_ADDR 0x8319
#define AUTO_NEG_RX_BASE_PAGE_15_0_ADDR 0x8330
#define AUTO_NEG_RX_BASE_PAGE_31_16_ADDR 0x8331
#define AUTO_NEG_RX_BASE_PAGE_47_32_ADDR 0x8332
#define AUTO_NEG_RX_MSG_PAGE_15_0_ADDR 0x8333
#define AUTO_NEG_RX_MSG_PAGE_31_16_ADDR 0x8334
#define AUTO_NEG_RX_MSG_PAGE_47_32_ADDR 0x8335
#define AUTO_NEG_RX_UF_PAGE_15_0_ADDR 0x8336
#define AUTO_NEG_RX_UF_PAGE_31_16_ADDR 0x8337
#define AUTO_NEG_RX_UF_PAGE_47_32_ADDR 0x8338

#define ANLT_LANE_SWAPPING_REFCLK 0x8440
